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DAC design questions (and doubts)

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mruzzi23

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Dear forum users,

For an exam about mixed state circuits, I have to design a 12 bit DAC in Virtuoso with some requirements:

1) 5 output channels
2) Vdd = 1.8V
3) SPI as interface (with 20 MHz clock), which can be made as a testbench
4) update rate (per channel) of 1KS/s
5) Settling time (1%) of analog out = 1us, with capacitive load of 10uF
6) Area < 0.05mm^2
7) Power consumption < 20 uW
8) Noise (in the DC-10KHz band) < 5uV (rms)

I already did the digital part with the SPI testbench (50 ns clock) which outputs a 16 bit serial string, with bits [15:13] which identify the output channel and bits [11:0] identifying the value (bit 12 is unused).
The serial string enters a shift register which shifts the string and creates a parallel string which is in turn given to a demux with 5 outputs that sends to the right channel the 12bit value.

This is my first time designing something like this so the level of complexity for me is a bit high.

My question is: are the the given specs enough for the dac output dual stage miller opamp design? Looks to me that I only have CL, ts, P and NSD specs, but I don't have any Gain, SR, GBW, GM and PM requirements, but again, I'm a novice in this field so I could be wrong.

Also, how can I satisfy the update rate requirement?

Thanks in advance.
 
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You have enough information, more or less. There are certain things not specified, like linearity or type of converter, etc. Question might be more if the specification makes sense. Since this is an exam project, I suppose that formulating a specification is a part of the task. You have to shortlist a few and judge if they can meet the specification and then start massaging it into a block description.

Some hints/comments/questions to guide you, but as indicated - you will have to do a bit of home work
  • Why do you need a two-stage miller-compensated opamp if you have such a large capacitive load?
  • What kind of DAC topology do you envision?
  • The gain is given by the required 12-bit resolution. To meet a 4096-level accuracy, your gain has to be at least higher than that (give-or-take).
  • The 1-% settling error within 1 us gives you the bandwidth and phase-margin requirements. Yet again, with the 10-us load you might not have to care that much about phase margin and can assume a single-pole system. A standard e^(t w0) calculation will suffice to give you the required pole location.
  • Slew rate would be given by current (power) over load capacitance and dictated by the 1-% requirement too. But assuming you need to toggle full swing in 1us would require you to output an SR at 0.99*Vdd/1us = Iout / 10 uF => Iout > 18 A (which is huge!) per opamp. So that puts another requirement on your architecture. (One specific architecture does not suffer from slew-rate limitations). Or your specification is wrong/incomplete. There is for example not clear to me why they specify in us when your sample rate is in ms.
Some juggling like that is required to start to understand the specification.
 
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Dear jjx,

Thanks for your reply, I'll try to answer to everything. I forgot to specify that the project is given from a company, reviewed by the professor and then sent to us. For this project in particular, the application would be the use of the DAC in implantable devices used for the monitoring of bio-electric signals from the brain and for the electrical stimulation of the CNS.

jjx said:
Why do you need a two-stage miller-compensated opamp if you have such a large capacitive load?
Click to expand...
The only architectures that our professor taught us to design are OTA, CS stage and then Miller Opamp, so I thought that opamp was the right choice. Is there another kind of amplifier that should be used with large cap loads?

jjx said:
What kind of DAC topology do you envision?
Click to expand...
I was thinking of using a simple R-2R ladder made with resistors. The other choice would be the other topology that we saw that was the charge redistribution, but the problem is that I don't know how to design it and how to make it work, since we didn't do any design for it and I can't find good sources on how to learn to do it (neither books nor online)

jjx said:
The gain is given by the required 12-bit resolution. To meet a 4096-level accuracy, your gain has to be at least higher than that (give-or-take).
Click to expand...
Oh, I think I understood. So having a gain > 4096 would gain up the DAC output, giving a 0-4095 volts scale, right?
jjx said:
The 1-% settling error within 1 us gives you the bandwidth and phase-margin requirements. Yet again, with the 10-us load you might not have to care that much about phase margin and can assume a single-pole system. A standard e^(t w0) calculation will suffice to give you the required pole location.
Click to expand...
Thanks for that tip, I'll take a look at it!

jjx said:
Slew rate would be given by current (power) over load capacitance and dictated by the 1-% requirement too. But assuming you need to toggle full swing in 1us would require you to output an SR at 0.99*Vdd/1us = Iout / 10 uF => Iout > 18 A (which is huge!) per opamp. So that puts another requirement on your architecture. (One specific architecture does not suffer from slew-rate limitations). Or your specification is wrong/incomplete. There is for example not clear to me why they specify in us when your sample rate is in ms.
Click to expand...
And that much of a current (that's really high) is strange for an application like the one I described before, right?
Ok, so there's also a possibility that the specs are not complete. I wanted to ask about that to my professor but he's not famous for being available :( that's why I'm trying to look as much as I can around the internet.

Thanks again
 
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mruzzi23 said:
I was thinking of using a simple R-2R ladder made with resistors.
Click to expand...
Perhaps you're already aware of all-in-one DAC chips available to convert given amounts of bits. 12-bits normal cost higher than $10. And the experimental stage may consume several chips.
 
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mruzzi23 said:
Dear jjx,
Thanks for your reply, I'll try to answer to everything. I forgot to specify that the project is given from a company, reviewed by the professor and then sent to us. For this project in particular, the application would be the use of the DAC in implantable devices used for the monitoring of bio-electric signals from the brain and for the electrical stimulation of the CNS.
The only architectures that our professor taught us to design are OTA, CS stage and then Miller Opamp, so I thought that opamp was the right choice. Is there another kind of amplifier that should be used with large cap loads?
I was thinking of using a simple R-2R ladder made with resistors. The other choice would be the other topology that we saw that was the charge redistribution, but the problem is that I don't know how to design it and how to make it work, since we didn't do any design for it and I can't find good sources on how to learn to do it (neither books nor online)
Oh, I think I understood. So having a gain > 4096 would gain up the DAC output, giving a 0-4095 volts scale, right?
Thanks for that tip, I'll take a look at it!
And that much of a current (that's really high) is strange for an application like the one I described before, right?
Ok, so there's also a possibility that the specs are not complete. I wanted to ask about that to my professor but he's not famous for being available :( that's why I'm trying to look as much as I can around the internet.
Click to expand...
  • "... and for the electrical stimulation of the CNS ..."
    • Ok, so either your DACs are for stimulation or for reference to the ADCs. Nevertheless, 10 uF sounds large in both cases...
    • And it might also be that they have an idea of what they need in an electrical way, but not fully sure of how it is implemented.
    • And yes, that will fry the nerves quite well and give seizure.
    • Here again, remember that response time of the cns is in the order of ms. µs does not make much sense tbh.
  • " ... Is there another kind of amplifier that should be used with large cap loads? "
    • Miller-compensated opamps are used to move the dominant pole inside the OTA and typically used for low(ish) capacitive loads (unless you add an additional source follower inbetween). Folded cascode would do in your case, I would guess. Beware of resistive load in the electrodes to the nerves.
  • " ... using a simple R-2R ladder made with resistors ... "
    • R-2R is dead simple to design, so probably an OK choice with the output buffer. You can drive it with current sources and also scale currents to obtain thermometer coding (in case you would have had a linearity requirement on your DAC).
    • A so called current-steering DAC does not need a buffer nor suffer from slew rate. But has limited swing and requires resistive termination (for your case).
  • "... So having a gain > 4096 would gain up the DAC output, giving a 0-4095 volts scale, right ..."
    • Yes. The closed-loop accuracy of the opamp would be 1/(1+1/A). A caveat here is once again that they have not specified DAC linearity and thus requirement might not be that strict to resolute the whole DAC range properly
  • my professor but he's not famous for being available :( that's
    • Haha :) That's a very common phenomena among professors :D
 
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jjx said:
  • "... and for the electrical stimulation of the CNS ..."
    • Ok, so either your DACs are for stimulation or for reference to the ADCs. Nevertheless, 10 uF sounds large in both cases...
    • And it might also be that they have an idea of what they need in an electrical way, but not fully sure of how it is implemented.
    • And yes, that will fry the nerves quite well and give seizure.
    • Here again, remember that response time of the cns is in the order of ms. µs does not make much sense tbh.
  • " ... Is there another kind of amplifier that should be used with large cap loads? "
    • Miller-compensated opamps are used to move the dominant pole inside the OTA and typically used for low(ish) capacitive loads (unless you add an additional source follower inbetween). Folded cascode would do in your case, I would guess. Beware of resistive load in the electrodes to the nerves.
  • " ... using a simple R-2R ladder made with resistors ... "
    • R-2R is dead simple to design, so probably an OK choice with the output buffer. You can drive it with current sources and also scale currents to obtain thermometer coding (in case you would have had a linearity requirement on your DAC).
    • A so called current-steering DAC does not need a buffer nor suffer from slew rate. But has limited swing and requires resistive termination (for your case).
  • "... So having a gain > 4096 would gain up the DAC output, giving a 0-4095 volts scale, right ..."
    • Yes. The closed-loop accuracy of the opamp would be 1/(1+1/A). A caveat here is once again that they have not specified DAC linearity and thus requirement might not be that strict to resolute the whole DAC range properly
  • my professor but he's not famous for being available :(that's
    • Haha :) That's a very common phenomena among professors :D
Click to expand...
Dear jjx,

First of all, happy holidays!
I had the chance to have a meeting with my professor, he told me that the specs are not wrong, he said that everything looks ok to him. But, I still have doubts.
I started to do some calculations and, as you said, the situation looks strange.

I'll start from the SR spec. We know that SR is equal to ΔV/Δt and also Iout/CL (page 4 of https://ww1.microchip.com/downloads/en/appnotes/00884a.pdf).
Keeping in mind that the opamp would never give me full swing, I suppose I'll have 1.6V (10% of the full swing value) as my ΔV and I know that my Δt is 1us.
I have a request on the power and so Iout will be P/V=20uW/1,8=10uA (approximately).

So SR in the first case is 1.6 V/us, while in the second case I have a SR of 1 V/s. Those specs are not converging to a common point, and that's driving me crazy.

To have a SR of 1.6 V/us, the calculations say that there should be a current of about ~16A and so a P of 28,5W: that seems really really high to me and still makes no sense, especially for this kind of application.

As for the PM, he said that 60º is the standard, so I have to use that spec.

He confirmed the gain spec tho.

And last thing he said, don't worry about the area request.
 
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