blooz
Advanced Member level 2
Here is the Icarus Verilog tutorial With Screen shots
A 4 bit Counter is used
//Save As counter.v
///////////////////////////
// 4 bit Counter
module counter(clk,q,reset);
input clk;
input reset;
output reg [3:0] q;
initial
begin
q=4'b0000;
end
always@( posedge clk)
begin
if (reset==1'b1)
q=4'b0000;
else
q=q+1;
end
endmodule
///////////////////////////
//Testbench
//Save as countertb.v
////////////////////////////////
`timescale 1ns/1ns
module countertb();
reg clk;
reg reset;
wire [3:0] q;
counter instance0(.clk(clk),.q(q),.reset(reset));
initial
begin
clk=1'b0;
reset=1'b1;
#10 reset=1'b0;
#1600 ;
$finish;
end
initial
begin
forever #20 clk=~clk;
end
initial
begin
$monitor("time=>%tns q=>%b",$time,q);
end
endmodule
//////////////////////////////////
A 4 bit Counter is used
//Save As counter.v
///////////////////////////
// 4 bit Counter
module counter(clk,q,reset);
input clk;
input reset;
output reg [3:0] q;
initial
begin
q=4'b0000;
end
always@( posedge clk)
begin
if (reset==1'b1)
q=4'b0000;
else
q=q+1;
end
endmodule
///////////////////////////
//Testbench
//Save as countertb.v
////////////////////////////////
`timescale 1ns/1ns
module countertb();
reg clk;
reg reset;
wire [3:0] q;
counter instance0(.clk(clk),.q(q),.reset(reset));
initial
begin
clk=1'b0;
reset=1'b1;
#10 reset=1'b0;
#1600 ;
$finish;
end
initial
begin
forever #20 clk=~clk;
end
initial
begin
$monitor("time=>%tns q=>%b",$time,q);
end
endmodule
//////////////////////////////////