vinay8287
Newbie level 1
Hi all.
Iam writting system verilog Assertion, i have come across with a problem in below code
$rose (req) |-> ##delay $rose (ack);
in tha above code variable delay i want to be chaging based on contents of some register, but am getting error : delay should be constant ---i tried passing delay through generate construct, since my register is 16 bit i have to generate 65535 gen blocks so its giving memory related issue,whts the solution??????
Iam writting system verilog Assertion, i have come across with a problem in below code
$rose (req) |-> ##delay $rose (ack);
in tha above code variable delay i want to be chaging based on contents of some register, but am getting error : delay should be constant ---i tried passing delay through generate construct, since my register is 16 bit i have to generate 65535 gen blocks so its giving memory related issue,whts the solution??????