How to resolve Timing Violation in back annotation with post gate level simulation?

Guess we see result of din setup timing violation.

FvM said:

Guess we see result of din setup timing violation.

Click to expand...

Thanks. Why does it make a setup violation? Is it setup violation possible that even though STA passed?

What is setup time?

coshy said:

Thanks. Why does it make a setup violation? Is it setup violation possible that even though STA passed?

Click to expand...

the question is not whether it passed or not. the question is whether what you call STA is what hey call STA. your simulation environment might have wildly different assumptions than the STA checks performed by the backend team.

D.A.(Tony)Stewart said:

What is setup time?

Click to expand...

ThisIsNotSam said:

the question is not whether it passed or not. the question is whether what you call STA is what hey call STA. your simulation environment might have wildly different assumptions than the STA checks performed by the backend team.

Click to expand...

From recommands, I have searched Standard Cell Librat DATASHEET.
Pin D has specific requirments.
setup (high ) 0.024997
setup (low) 0.034080

but when I check, sc9mcpp84_14lpu_base_lvt_c16.v there's are defined ARMSETUPTIMEandARMSETUPTIMEandAR_HOLD_TIME $setuphold(posedge CK &&& (ENABLE_NOT_D_AND_NOT_RAND_SI == 1'b1), negedge SE, ARMSETUPTIME,ARMSETUPTIME,ARM_HOLD_TIME, NOTIFIER, , ,dck,dSI);

From Here I'm confused that ARM_SETUP_TIME defined 1.0 and AR_HOLD_TIME is defined 0.5.

Do I need to modify Standard Cell Library verilog model defines as DATASHEET?

dout goes 'x' even when there's no change in din w.r.t second clk edge. so, this might not be a real timing violation.
Or another scenario is you actually have a 2-stage synchronizer cell and not a simple DFF, hence dout which is output of second stage will be =1 for one cycle and 'x' in the following.

coshy said:

From recommands, I have searched Standard Cell Librat DATASHEET.
Pin D has specific requirments.
setup (high ) 0.024997
setup (low) 0.034080

but when I check, sc9mcpp84_14lpu_base_lvt_c16.v there's are defined ARMSETUPTIMEandARMSETUPTIMEandAR_HOLD_TIME $setuphold(posedge CK &&& (ENABLE_NOT_D_AND_NOT_RAND_SI == 1'b1), negedge SE, ARMSETUPTIME,ARMSETUPTIME,ARM_HOLD_TIME, NOTIFIER, , ,dck,dSI);

From Here I'm confused that ARM_SETUP_TIME defined 1.0 and AR_HOLD_TIME is defined 0.5.

Do I need to modify Standard Cell Library verilog model defines as DATASHEET?

Click to expand...

are you using an SDF file?

ThisIsNotSam said:

are you using an SDF file?

Click to expand...

Yes, and use it $back_annotation(my_sdf,...,)

Then you need to apply your engineering skills and understand if this a single path failing or several (all?) paths everywhere. This would indicate whether it is a timing problem or a simulation setup problem.

Also make sure the verilog code you are using for the std cells is appropriate for what you are doing. ARM, if I am not mistaken, has a lot of switches that you can turn on/off and the model will change accordingly. You have to make sure you are not using the unit model, where every gate takes 1 time unit to propagate a signal. This will never give you a timing-aware simulation.